Model Based Test Generation for Processor Verification

Yossi Lichtenstein, Yossi Malka and Aharon Aharon, IBM Israel Science and Technology

A few simple Expert-System techniques have been invaluable in developing a new test program generator for design verification of hardware processors. The new generator uses a formal declarative model of the processor architecture; it allows generation of test programs for a variety of processors without duplication of effort. A heuristic knowledge base representing knowledge about testing techniques allows generation of incisive tests. This knowledge base captures information that until now has been kept by experts and has not been formally documented. Furthermore, the complexity, changeability and non-visibility of architectural details and testing knowledge within previous test generation systems have been reduced by the new data-bases. A search and backtracking mechanism comprises the generator itself and allows the generation of complex test programs. IBM has invested several million dollars in developing the Model-Based Test-Generation system. Several architectures have been modelled by the system. They include an AS/400 CISC processor, a floating point unit of an S/390 computer, a vector floating point unit, and four implementations of a PowerPC-like architecture. The first silicon realizations of two of the designs have already been shown to be equivalent to the architectural specification. Other designs are still under testing. There are also first indications that using the new technology reduces verification period and decreases time to market: The verification of a high-end RISC processor required six calendar months, in contrast to fifteen months needed for verifying a simpler processor using a previous test generation technology.


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